As a technique of increasing the density of a memory without depending on lithography, structures such as a structure in which a one-time-programmable (OTP) element is sandwiched between multiple interconnection layers and a structure in which a plurality of NAND flash memory layers are formed by repeating epitaxial growth of silicon films have been proposed. However, these structures have the problem that the number of times of lithography increases as the number of stacked layers increases. Therefore, a collectively processed, three-dimensionally stacked memory has been proposed as a technique replacing these structures.
In this three-dimensionally stacked memory, a hole (memory hole) is formed at once through a plurality of electrodes stacked on a semiconductor substrate, and a memory film is formed on the inner walls of the hole. After that, the hole is filled with a polysilicon film (silicon pillar). Consequently, a memory string including a plurality of memory elements connected in series in the stacking direction can be formed at one time. This makes it possible to implement a memory for which the number of lithography steps hardly increases even when the number of layers to be stacked is increased.
In the three-dimensionally stacked memory as described above, the insulating film (memory film) of the memory element is formed on the inner walls of the hole before the formation of a polysilicon film serving as a channel. After that, only the insulating film formed on the bottom of the hole must be removed in order to supply an electric current to the memory string by improving the connection between the polysilicon film and, for example, a source line (for example, polysilicon) positioned below the polysilicon film. This imposes the technical limitation that it is necessary to use a memory film configuration that can withstand processing with diluted hydrofluoric acid to remove the insulating film from the bottom. When using, for example, the multilevel-cell technology as a method of further increasing the density of the three-dimensionally stacked memory, this limitation increases the difficulty in development of the memory film configuration, so the situation is not necessarily favorable.
To improve this situation, a three-dimensionally stacked memory using a U-shaped silicon pillar as a memory string has been proposed. This U-shaped silicon pillar includes a pair of columnar portions and a connecting portion for connecting the lower ends of these columnar portions. The upper portion of one of the pair of columnar portions is connected to a bit line, and the upper portion of the other columnar portion is connected to a source line. That is, there is no polysilicon-polysilicon contact on the bottom of a memory hole, and this obviates the removal of an insulating film from the bottom. This can increase the degree of freedom of the memory film configuration.
On the other hand, to reduce the chip occupation ratio of the three-dimensionally stacked memory cell array as described above and a control circuit for controlling the array, a technique of forming the control circuit on a semiconductor substrate immediately below the memory cell array has been proposed. If the control circuit is formed below the memory cell array, however, the control circuit, for example, a sense amplifier and a bit line interconnection must be connected by a contact plug formed in a memory cell array end portion. That is, the bit line interconnection is connected to a bit line extension formed below the memory cell array via the contact plug formed in the memory cell array end portion, and the bit line extension is connected to, for example, a transistor (sense amplifier) formed on the semiconductor substrate.
This structure poses the problems that, for example, a fine interconnection layer (the bit line extension) equivalent to a bit line is necessary below the memory cell array, a region having a considerable size is necessary in the memory cell array periphery in order to form a deep contact, and the bit line practically gets longer to increase the bit line capacitance, thereby affecting the operating speed.